Semiconductor device fabrication involves a number of processing steps including implant steps, deposition steps, and metallization steps. Many of these steps include forming patterns in a photoresist layer using a mask. The light from an exposure system shines through the mask which blocks light in some areas and lets it pass in others. The light results in chemical changes to exposed portions of the photoresist to form a pattern.
The patterned photoresist can then be used to create a layer on the wafer. For example, for a metallization layer, metal can be deposited on the patterned photoresist and the later removal of the photoresist forms the patterned metallization layer.
The masks are created using computer design tools from a circuit design. These design tools, among other things, optimize the masks so that the integrated circuit design can be placed on a small wafer.
A chip is often revised after initial manufacture for purposes of correcting minor design defects, or otherwise making minor changes, by modifying a subset of the mask layers comprising the design. As part of the revision of the chip, the revision level identifier is also updated.
The revision level of the chip is commonly contained in one or more read only registers, some accessible by system software and others accessible by Joint Test Action Group (JTAG), the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. When the revision level of a chip is synthesized, an arbitrary number of masks are used to create the bit pattern making up the hardwired content. This often forces changes to masks exclusively for the purpose of updating the content of one or more revision level registers. Revising masks exclusively for the purpose of updating the revision level registers is undesirable since creating a new mask results in additional expense.